Although mathematical functions can be performed in an arithmetic logic unit using only addition, subtraction, and shift operations, some processors, and in particular some numeric coprocessors or floating point units (FPUs), incorporate multiplier circuits in the arithmetic (or execution) unit to more efficiently perform certain multiplication and other mathematical functions such as division, square root, and transcendentals (sine, cosine, etc.).
Without limiting the scope of the invention, this background information is provided in the context of a specific problem to which the invention has application: reducing the amount of circuitry required to implement the arithmetic unit of an FPU.
FIG. 1a illustrates a conventional implementation of an FPU arithmetic unit incorporating a multiplier circuit. The arithmetic unit includes two channels: a multiplier channel and an adder channel. The multiplier channel includes a Booth-recoded multiplier that provides redundant outputs, and a converter for converting those redundant outputs into the final nonredundant result by performing a full tipple carry operation. The adder channel includes a barrel shifter for aligning the input operands, an adder circuit, and a normalizer circuit for performing a shift operation to eliminate leading zeros and provide a normalized output.
FIG. 1b illustrates an FPU arithmetic unit in which the converter circuitry has been eliminated from the multiplier channel. Instead, the redundant outputs of the multiplier circuit are input to a three input adder. For multiplication, the two operands are input to the multiplier and, for each pass through the multiplier, the adder performs addition with a full ripple carry (including, if necessary, partial product addition). For addition, one operand is input to the multiplier, multiplied by one, and input to the adder, while the second operand is aligned in the barrel shifter (right or left shift) and also input to the adder which performs the addition of the two operands.
Thus, the design for the arithmetic unit in FIG. 1b is able to eliminate the converter by using a somewhat more complex three input adder and adding some associated control logic. However, this design still includes the barrel shifter in the adder channel which adds a substantial amount of logic and complexity to the design of the arithmetic unit.
Accordingly, a general object of the invention is to provide a design for an arithmetic unit that requires less circuitry than current designs, specifically by eliminating the barrel shifter in the adder channel.